As a method of bridging double system buses that are independent of each other, there are known an arbitrating apparatus disclosed in Japanese Patent Published Application No. 6-89257 (1994), a bus system and a bus bridge method in Japanese Patent Published Application No. 6-164594 (1994), a bus bridge for information processing apparatus in Japanese Patent Published Application No. 6-37768 (1994), and DEC Chip 21050 PCI-to-PCI Bridge Data Sheet (First Edition, December 1993). All are directed to realize a bus bridge function by that a bus bridge includes an arbitration function of at least one bus.
FIG. 12 is a diagram showing a computer system in which two buses are connected by a bus bridge apparatus. A first bus 1210 is independent of a second bus 1220. A first master device 1211, a first slave device 1212, a first arbiter 1213 are connected to the first bus 1210. Second master devices 1221, 1224, a second slave device 1222 and a second arbiter 1223 are connected to the second bus 1220. Between the first bus 1210 and the second bus 1220, a bus bridge apparatus 1201 is disposed. In order that the first master bus 1211 accesses the second slave device 1222, the bus bridge apparatus 1201 serves as a slave device on the first bus 1210 to respond to the first master device 1211, and, at the same time, serves as a master device on the second bus 1220 to access the second slave device 1222. Similarly, in order that the second master device 1221 accesses the first slave device 1212, the bus bridge apparatus 1201 serves as a slave device on the second bus 1220 to respond to the second master device 1221, and, at the same time, serves as a master device on the first bus 1210 to access the first slave device 1212.
Assume that the aforesaid two accesses occur at the same time. On the first bus 1210, since the first arbiter 1213 has assigned bus access right to the first master device 1211, the bus bridge apparatus 1201 cannot be assigned bus access right as a master device to gain access from the second master device 1221 to the first slave device 1211, until access of the first master device 1211 has been completed.
On the second bus 1220, since the second arbiter 1223 has assigned bus access right to the second master device 1221, the bus bridge apparatus 1201 cannot be assigned bus access right as a master device to gain access from the first master device 1211 to the second slave device 1222, until access of the second master device 1201 has been completed. Therefore, both buses' operations have no progress, i.e., a so-called deadlock condition occurs.
To solve this problem, for example, processing has been conducted to prevent access right from being assigned to the first master device 1211 and the second master device at the same time, by disposing an arbiter inside a bridge to give preference to the bus 1210 or 1220.
In an independent bus in which access time-out exits, when conducting a slave access across the bus, it is difficult to start access in another bus when a bus to which access is desired is busy. Accordingly, time-out is likely to occur before a cycle ends. To avoid this, it is necessary to complete access within a given time. This has been solved by disposing an arbiter inside a bridge and raising the precedence of a bus bridge as a master device.
However, provided that an arbiter is disposed inside a bridge, independent systems, each having an arbiter, cannot be connected under the present systems. It is thus necessary to change system design.